The present invention generally relates to a method for reducing transistor series resistance. In particular, the present invention relates to a method for reducing transistor series resistance by nitrogen implantation into an nLDD/Source/Drain extension region of the transistor.
Complimentary metal-oxide semiconductor (CMOS) designs have become popular in logic circuit designs for numerous reasons including their noise immunity, operability over wide voltage ranges and other properties. Such advantages outweigh the fact that oftentimes a greater number of transistors is necessary on a chip for equivalent logic functions as compared to other field effect transistor FET technologies.
Two types of transistors formed in a complimentary metal-oxide semiconductor (CMOS) fabrication process are NMOS and PMOS. PMOS transistors and NMOS transistors each have four terminals (or connection points): a gate terminal, a source terminal, a drain terminal, and a bulk terminal. Electric current flows from the source terminal to the drain terminal of a transistor when a voltage applied to the gate terminal has either a higher or lower value than the voltage applied to the source terminal, depending on the transistor type. A PMOS transistor is a transistor in which current flows if the voltage applied to the gate terminal is lower than the voltage applied to the source terminal. An NMOS transistor is a transistor in which current flows if the voltage applied to the gate terminal is higher than the voltage applied to the source terminal. The bulk terminal is connected either to the source terminal of the transistor or to an appropriate bias voltage.
In both the PMOS transistor and NMOS transistor, the difference in voltage between the gate terminal and the source terminal must be larger in absolute value than a certain voltage before current will flow between the source and drain terminals. This particular voltage is commonly referred to as a xe2x80x9cthresholdxe2x80x9d voltage and is the voltage required to form a channel between source and drain diffusion regions in the PMOS transistor or the NMOS transistor. As is known, the respective transistors are formed on a substrate by diffusing impurities into two regions (a drain diffusion region and a source diffusion region). The two regions are separated by a distance of undiffused substrate material called a channel, over which the gate terminal is constructed. By applying a voltage to the gate terminal of the transistor, the channel is energized such that current may flow between the source diffusion region and the drain diffusion region.
An impurity well of opposite conductivity type is required for one of the transistors of each complementary circuit. These additional structures occupy space on the chip and thus contribute to the incentive for miniaturization of the transistors formed thereon.
Several limitations on miniaturization of field-effect transistors have been encountered. As a conduction channel is made small, several adverse effects on transistor performance occur such as series resistance and/or hot electron carrier effects.
The series resistance of an FET is a function of both the cross-sectional area and length of the conduction channel. It is desirable to limit the depth which the conduction channel extends into the substrate in order to limit the voltage which is needed to control the FET as well as to limit leakage and punch-through effects. However, the use of such shallow junctions causes the series resistance to increase. Series resistance must be maintained at a low value in order not to degrade the extrinsic transconductance of the FET.
In general, the greater the extrinsic transconductance of the FET, the faster the circuit performance obtained. Low series resistance is often achieved by siliciding (i.e., forming a metal silicide at a metal-silicon interface) the source and drain or selectively depositing metal such as tungsten on the source and drain areas. However, this is difficult to achieve consistently for shallow junctions. The silicidation consumes surface silicon and can give rise to increased leakage current. Self-aligned silicides such as titanium disilicide are frequently formed on source/drains to lower sheet resistivity. However, a heavily phosphorus-doped n-type source/drain (to minimize the silicon/silicide contact resistance) leads to a deep source/drain region. Contrarily, an arsenic doped source/drain region will not be deep enough to avoid consumption of the shallow arsenic-doped silicon during silicidation leading to high junction leakage or spiking by the silicide through to the substrate if (as in CMOS structures) only low drive-in temperature can be used because of high diffusivity of boron implants in other parts of the integrated circuit.
Increases in series resistance cannot be fully compensated by decreasing the length of the conduction channel. While a short conduction channel is desirable both for miniaturization as well as low series resistance, when the conduction channel is reduced below 1 xcexcm, the threshold voltage is reduced due to charge sharing with the drain junction. Similarly, leakage and punch through effects are increased. The leakage or xe2x80x9coffxe2x80x9d state current is increased due to the reduced threshold voltage, resulting in increased standby current for the chip. When the threshold voltage is lowered by a large amount, the device is said to be punched through. While the threshold reduction can be limited by reducing the depth of the conduction channel, reduction of depth of the channel degrades series resistance, as discussed above.
Thus a difficulty in the fabrication of small-geometry metal-oxide-silicon transistors is that if the source/drains are doped to a level high enough to give a reasonable low series resistance, the magnitude of the electric field in the channel adjacent the drain during the on-state will be so high that hot carriers and impact ionization effects become a nuisance.
Consequently, there is a need in the art for a method for fabricating CMOS devices and the like which reduces series resistance without increasing leakage and punch through effects.
By introducing a nitrogen implanting step in connection with a conventional n-type dopant implanting step (e.g., arsenic implanting step), a CMOS device results having low series resistance, reduced hot carrier effects and avoids a significant increase in source/drain (S/D) extension overlap (i.e., horizontal spreading of the implant). Contrary to conventional CMOS fabrication techniques where increasing dopant concentration results in lower sheet resistance, the nitrogen implantation of the present invention does not result in a deeper junction as a result of the increase in dopant. If a conventional dopant (e.g., arsenic or phosphorus) concentration is increased to lower sheet resistance, a deeper junction results. Deeper junctions result in bad roll-off, makes the device more difficult to control, and may result in punch through effects which are undesirable. The present invention avoids these negative effects because the addition of the nitrogen dopant does not increase the depth of the junction which is typically the case with conventional n-type dopants such as arsenic. The nitrogen implantation provides for reduced series resistance without increasing junction depth and reduced hot carrier effects as compared to using a conventional n-type dopant.
In accordance with one specific aspect of the present invention, a method of fabricating a complimentary MOS transistor having a source/drain extension region is provided, including the step of: implanting nitrogen into the source/drain extension region.
According to another aspect of the present invention, a method of fabricating a complimentary MOS transistor is provided including the steps of: providing a substrate having field oxide regions thereon; providing an p-well region by masking a portion of the substrate with a first photoresist layer and implanting p-well dopants; providing an n-well region by masking the portion of the substrate designated for the p-well region with a second photoresist layer and implanting n-well dopants; forming a polygate structure on the n-well and p-well regions; masking the n-well with an n-channel LDD mask; implanting an n-implant into the p-well region; and implanting nitrogen into the p-well region.
Another aspect of the present invention provides for a complimentary MOS transistor including a lightly doped region which was implanted with nitrogen.
In accordance with another aspect of the present invention, a method of fabricating a field effect transistor having a source/drain extension region is provided, including the step of: implanting nitrogen into the source/drain extension region.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.